Content addressable memory cells are used, for example, to determine a correspondence or match between first data stored in the cell and second data presented as input to the cell. The input data can be made up of a header of a data packet containing the address of a remote computer of a computer network, for example. The memory cells of a CAM matrix store the addresses of all of the computers of the network. The memory matrix then determines if there is a correspondence or match between the address conveyed by the header and the address of the computers in the network.
To achieve this, a CAM matrix is made up of a network of individual CAM cells. FIG. 1 shows the general architecture of a conventional CAM cell. Such a cell comprises a first memory circuit 10, a second memory circuit 12 and a comparison circuit 14. The first and second memory circuits 10 and 12 are for storing a data value and a masking value, respectively. The masking value is used to enable or disable the comparison circuit 14. The first and second memory circuits 10, 12 are respectively addressable by word lines WLD and WLM, and by bit lines BLT and BLF.
The comparison circuit 14 is used to compare data signals dt and df corresponding to a data value stored in the first memory circuit 10 with data signals ct and cf presented at the input of the memory cell. When the second memory circuit 12 stores a value for enabling the CAM cell, the comparison circuit 14 carries out the comparison between a value presented at the input of the cell and a value stored in the memory in the first memory circuit 10.
In the case of a correspondence, the voltage level of a correspondence line C at the output of the comparison circuit 14 remains unchanged. In contrast, if there is no correspondence, the voltage level on the correspondence line C switches, for example, from the upper level to the lower level.
FIG. 2 shows a physical embodiment of a conventional CAM cell on a silicon substrate. In the illustrated example, a CAM cell comprises eighteen transistors to create the first memory circuit 10, the second memory circuit 12 and the comparison circuit 14.
The first memory cell 10 comprises six transistors; four transistors N1, N2, P1 and P2 for storing data and two access transistors T3 and T4. Likewise, the second memory circuit 12 comprises four storage transistors N3, N4, P3 and P4 as well as two access transistors T1 and T2. The comparison circuit 14 also comprises six transistors; four comparison transistors N5, N7, N8 and N10 and two enabling transistors N6 and N9.
For the purpose of being able to drive the comparison circuit 14, the output of the second memory circuit 12 is connected to the enabling transistors N6 and N9 via a polysilicon track MT. More particularly, the gates of the transistors N4 and P4 are connected via the track MT to the gates of the transistors N6 and N9. Likewise, to transfer the data values dt and df from the first memory circuit 10 to the comparison circuit 14, the gates of the storage transistors N1, P1 and N2, P2 are connected to the gates of the comparison transistors N5 and N8, respectively.
As illustrated in FIG. 2, the traditional implementation of a CAM cell has a number of considerable disadvantages. First, the polysilicon tracks MT at the comparison circuit 14 in particular, have a number of angles, particularly due to the fact that the transistors of the memory circuits and of the comparison circuit are formed in different directions, the former vertically and the latter horizontally, for example. The configuration of the polysilicon tracks is then largely detrimental to the density of the installation, and makes checking the transistors relatively difficult.
Furthermore, the configuration of the junctions of the transistors generate, in this type of installation, a stress at the lateral STI (shallow trench isolation) regions which tends to degrade the properties of the transistor. Yet, it is not possible to increase the size of the transistors, and in particular, the length of the channel without dismantling the whole cell.